Special SSO Seminar - Sri Vadlamani (MIT) - “Building principled analog hardware for computing”

Special Solid State & Optics Seminar 

sponsored by “The Flint Fund Series on Quantum Devices and Nanostructures”

Sri Vadlamani, Massachussetts Institute of Technology

Date : Friday, July 14th 

Time: 10:30 AM 

Location: Becton 227 or  via Zoom

Zoom Link: https://yale.zoom.us/j/94535498746.

Building principled analog hardware for computing  

Principled hardware for optimization: Combinatorial optimization is of great interest in operations research, but several important problems in this field are known to be NP-hard. Conventional digital solvers use either provable approximation algorithms or inspired heuristics. Recent papers have demonstrated high-quality approximate solvers built from coupled bistable oscillator networks for the NP-hard Ising problem. While the dynamics of these hardware systems are often derived in the literature, it has so far not been clear why exactly these optimizers obtain the high-quality results that they do. Our work fills this gap in the theory by revealing a deep connection between the physics of bistable oscillators and the mathematics of optimization — the dynamical equations of coupled signal-pump parametric oscillator networks are exactly equivalent to the well-known primal-dual method of Lagrange multipliers for constrained optimization.
 
Principled hardware for machine learning: The exponential rise of deep learning over the past decade has resulted in massive present-day neural networks with voracious energy appetites. Analog neural network accelerators promise tremendous energy and time savings but one still needs to answer a major criticism of analog circuits — that they can be unreliable as general purpose computers because of their sensitivity to even tiny hardware errors. A setting that exemplifies this difficulty is that of model deployment — in the conventional digital case, neural network training is performed only once and the resultant model is reliably deployed to any number of edge devices with no device-specific modification. In the analog case, however, individual chip faults render direct model deployment unreliable. Our work introduces a one-time error-aware software training technique based on engineering corner analysis that solves this problem and brings analog neural networks into the same league as digital neural networks in terms of ease of model training and large-scale deployment, even in the presence of large hardware errors.
 
 

Biography: Sri is a postdoctoral associate in Prof. Dirk Englund’s Quantum Photonics Group at MIT. His research interests lie in the investigation of the interplay between physical principles, machine learning, and optimization, with his current focus being the design of novel energy-efficient hardware for computing. He obtained a Ph.D. in Electrical Engineering and Computer Sciences from the University of California, Berkeley in 2021. His Ph.D. work was focused on the theory of energy-efficient devices and systems: spectroscopic lineshape theory for tunnel transistors, and physics-based combinatorial optimization solvers. Before that, he received his Bachelor of Technology degree (with honors) in Electrical Engineering, with a minor in Physics, from the Indian Institute of Technology Bombay (IIT Bombay), India, in 2016.

Event time: 
Tuesday, July 11, 2023 - 6:30pm
Hosted By: 
Owen Miller